74HC138
3-to-8 Line Decoder/Demultiplexer
Pinout
Description
The 74HC138 is a high-speed CMOS 3-to-8 line decoder/demultiplexer. It accepts a 3-bit binary address on inputs A0–A2 and activates one of eight active-low outputs (Y0–Y7). Three enable inputs (E1, E2 active-low, E3 active-high) allow cascading and easy expansion to larger decoders.
Pin Descriptions
| # | Name | Type | Description |
|---|---|---|---|
| 1 | A0 | input | Address input bit 0 (LSB) |
| 2 | A1 | input | Address input bit 1 |
| 3 | A2 | input | Address input bit 2 (MSB) |
| 4 | ~E1 | enable | Enable input 1, active low |
| 5 | ~E2 | enable | Enable input 2, active low |
| 6 | E3 | enable | Enable input 3, active high |
| 7 | ~Y7 | output | Output 7, active low |
| 8 | GND | power | Ground |
| 9 | ~Y6 | output | Output 6, active low |
| 10 | ~Y5 | output | Output 5, active low |
| 11 | ~Y4 | output | Output 4, active low |
| 12 | ~Y3 | output | Output 3, active low |
| 13 | ~Y2 | output | Output 2, active low |
| 14 | ~Y1 | output | Output 1, active low |
| 15 | ~Y0 | output | Output 0, active low (selected when A=000) |
| 16 | VCC | power | Supply voltage |
Truth Table
| E1~ | E2~ | E3 | A2 | A1 | A0 | Y0~ | Y1~ | Y2~ | Y3~ | Y4~ | Y5~ | Y6~ | Y7~ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| H | X | X | X | X | X | H | H | H | H | H | H | H | H |
| X | H | X | X | X | X | H | H | H | H | H | H | H | H |
| X | X | L | X | X | X | H | H | H | H | H | H | H | H |
| L | L | H | L | L | L | L | H | H | H | H | H | H | H |
| L | L | H | L | L | H | H | L | H | H | H | H | H | H |
| L | L | H | L | H | L | H | H | L | H | H | H | H | H |
| L | L | H | L | H | H | H | H | H | L | H | H | H | H |
| L | L | H | H | L | L | H | H | H | H | L | H | H | H |
| L | L | H | H | L | H | H | H | H | H | H | L | H | H |
| L | L | H | H | H | L | H | H | H | H | H | H | L | H |
| L | L | H | H | H | H | H | H | H | H | H | H | H | L |